Instruction Set Architecture

Whenever CPU designers decide to release a completely new, clean-sheet processor, they first decide upon the structure of the low-level programming that will be used to write software for the chip. This low-level structure includes a list of the operations the CPU will perform, what parameters each operation will accept, what registers will be available, and how the processor will interface with memory and I/O devices. A completed paper design for how the CPU will operate becomes its Instruction Set Architecture (ISA).

Once a CPU goes into production, various improvements can be made without changing the fundamental ISA. Newer CPUs can be sold later as upgrades to the original model, and software written for the previous version of the CPU will continue to run on the new one.

Video Lecture

The Abstraction and the Handcuff

Prior to the commoditization of off-the-shelf processors, computer software had to be tailored for the specific model of CPU present inside the computer. Each subsequent revision to the design of the computer necessitated substantial modifications to each program that would run on the system. Software was not an independent commodity, as both the computer hardware and its operating software had to be developed and sold together as a coupled unit. Moreover, programs had to be written using the low-level instructions that the hardware was designed to execute – a tedious task at best.

By 1952, researchers were working to improve the process of programming computers. It was realized that a program could be written in the low-level instruction language used by the computer, which would convert a more readable form of the program into machine instructions that could be executed by the system. The first of these efforts was AUTOCODE, written by Alick Glennie for the Mark I.¹ In the same year, Grace Hopper described a more advanced system with a reusable library of subroutines for the UNIVAC, creating the first compiler.² With these advances, it became possible to write programs using a high-level language, instead of having to write individual machine instructions.

As computer systems became commercialized, companies realized the competitive value of being able to sell hardware upgrades to existing customers. In order for these upgrades to be practical, customers had to be able to continue to run their existing software applications. CPU designers therefore added a layer of abstraction between the physical details of the processor and the machine language that it could understand, enabling compilers to be written who whole families of compatible processors. This abstraction is the Instruction Set Architecture (ISA) that the processor is engineered to follow. Programmers can write code that uses compilers and libraries designed for the ISA, and any CPU that implements the ISA will be able to execute the resulting software.

One side effect of this abstraction results from the fact that no ISA design is ever perfect. Decisions that are made early in the lifetime of a long-lived ISA must be carried through with each successive improvement in the underlying hardware. For example, the modern x86_64 architecture shares some design decisions that date back to the original x86 ISA for Intel 8086 CPU, released in June 1978.³ Whether or not those design decisions would be good ideas today, choices from the 1970s still affect modern AMD and Intel CPUs, enabling them to retain compatibility with old software. Modern x86_64 CPUs are effectively “handcuffed” to these early decisions by marketing needs. A completely new ISA might be more efficient and cleaner to implement, but a major factor driving sales of this architecture is its ability to continue running legacy applications.

Complex and Reduced Instruction Sets

Early in the development of processors, when code had to be written by hand using machine instructions, it was desirable to create machine instructions that could perform multiple steps, even if individual steps took more than one clock cycle to complete. By making the hardware a bit more complicated, the drudgery of machine-level programming was slightly reduced. Since the development of compilers and high-level languages occurred in parallel with advancements in hardware, both of which occurred as commercial use of computing expanded, these original machine instructions survived even as the amount of machine code written by hand decreased.

In 1974, an IBM researcher named John Cocke designed an ISA for a product designed to run telephone exchanges.⁴ This ISA was simplified, and the resulting hardware made faster, by designing the ISA in such a way that each instruction took only one clock cycle to execute. To make this design work, the total number and complexity of supported instructions had to be reduced, which would not have caused significant issues as long as most of the code for the system could be written in a higher-level language and compiled to the more verbose set of machine instructions. University of California researcher David Patterson used this idea to design a system called the RISC I in the early 1980s, coining the term Reduced Instruction Set Computer (RISC) in the process.⁵

Designs using larger instruction sets were then termed Complex Instruction Set Computer (CISC) architectures in retrospect. Since the Intel 8086 CPU became commercially available in 1978, its development was too early to adopt a RISC design, and the modern x86_64 ISA remains a CISC design today. However, RISC designs are commercially available, as noted in the next section. In practice, nearly all modern software is written in some type of high level language, which is then translated to machine instructions by a compiler. Complex instruction sets require more complicated compilers to create optimal machine-level code. In contrast, compilers for RISC systems can be simpler and easier to implement.

Notable Instruction Set Architectures

Processors using several ISAs are commercially available as of late 2020, with the x86_64 and Arm ISAs dominating the general-purpose computing market. x86_64, originally known as AMD64, is a CISC ISA developed by AMD. This architecture was based on the Intel x86 ISA, which itself descended from the Intel 8086.⁶ Most desktop, laptop, and server computers as of late 2020 use the x86_64 ISA. Intel and AMD continue to be the dominant manufacturers of x86_64-compatible CPUs.

Originally named the Acorn RISC Machine, the Arm ISA is a RISC architecture developed by Arm Holdings, with chips manufactured by various licensees.⁷ Processors based on the Arm architecture are widely used in mobile phones and tablets, due to their significantly greater power efficiency compared to x86_64. Several laptop devices also use this ISA, including some Mac systems using the Apple M1 CPU announced in late 2020.⁸ Various revisions of the Arm ISA are still in production, ranging from soft-float chips used in embedded devices to 64-bit hard-float designs for general-purpose computing.

A potential Arm competitor is emerging as of late 2020: RISC-V.⁹ Unlike Arm or x86_64, RISC-V is an open design that can be used by manufacturers without having to pay royalties or license fees. Several processor models based on RISC-V are in early development with limited commercial availability at the time of this writing. However, an open source CPU design has the potential to have the same disruptive impact on hardware as the open source software movement has had on software.

Seeking to capitalize on open hardware at the other end of the performance spectrum, IBM has opened the POWER ISA, which was formerly a proprietary design.¹⁰ POWER is a RISC architecture aimed at high performance computing, and CPUs with this architecture are commercially available for both workstations¹¹ and servers.¹² Coastal Carolina University has some servers using this ISA in the main campus data center.

Various other instruction set architectures have been created, some of which are still commercially available, at least in limited cases. One such architecture, MIPS, found some use in early game consoles, a few tablets, and some other embedded devices. However, the commercial future of this RISC architecture appears dubious after the company behind it randomly reversed its licensing plan and confused or alienated potential customers.¹³

Notes and References

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.